1. Field of the Invention
The disclosed invention relates to solid state memory elements and to matrix arrangements of such memory elements for performing a comparison function.
2. Description of the Prior Art
Memory elements, that utilize the hysteresis effects observed with certain insulators in field effect transistors are well known in the prior art. The usual form of transistor memory element is an insulated-gate field effect transistor in which the silicon dioxide gate insulator is replaced by a double insulation layer, typically a layer of silicon dioxide near the semiconductor and a layer of silicon nitride over the silicon dioxide. This structure is commonly referred to as a metal-nitride-oxide semiconductor transistor (MNOS transistor). The device is operated as a memory device by controlling the threshold voltage through the application of a polarizing voltage between the gate electrode and the source and drain electrodes for a known time interval. As a result of the polarizing voltage, a charge is formed in the insulator between the gate electrode and the substrate such that a voltage appears between the gate and source electrodes which determines the threshold voltage for the device. The threshold voltage of the memory element is therefore controlled in accordance with the polarizing voltage to establish a memory condition in the element. The memory condition, of threshold voltage, is initialized or erased by applying an erasing voltage of opposite polarity with respect to the polarizing voltage for a predetermined time interval. The hysteresis of MNOS devices is associated with the existence of traps near the silicon dioxide-silicon nitride interface, the threshold voltage of the transistor being influenced by the charged state of the traps as described in U.S. Pat. No. 3,652,324 to Chu et. al. and a publication by J. R. Szedon entitled "An Insulated Gate Field Effect Transistor Non-volatile Memory Element Using Tunnel Trapping In A Diode Layer Dielectric" which appeared in Westinghouse Scientific Report 68-1 F 1-SOISS-RI (1968).
It is also known in the prior art to employ such MNOS memory devices in circuitry so as to perform computations in accordance with the input voltage to output current transfer function of the MNOS memory elements. For example, U.S. Pat. No. 3,864,558 to Ka-Chung Yu describes the control of a memory element comprised complementary connected MNOS devices to compute the square of the deviation of an input signal with respect to a reference signal. In this case, a polarizing voltage is applied to program the memory element by controlling the voltage-current transfer function. After the memory element is programmed, a voltage corresponding to the input signal is applied between the gate and source electrodes of the memory element and the voltage of the input signal provides a saturation drain current corresponding to the square of the deviation between the voltages that represent the reference and input signals. The memory element is erased by applying a voltage of opposite polarity from the polarizing voltage for a sufficient time to return the threshold voltage to its initial value.
Also in the prior art are circuits employing a matrix of memory elements comprised of MNOS devices for comparing a plurality of input signals with a plurality of reference signals such as is described in U.S. Pat. No. 3,845,471 to H. J. P. Reitbeock et al. Briefly, the memory elements of the matrix are selectively programmed either individually or collectively by applying a polarizing voltage for a time corresponding to the various reference signals. The polarizing voltage programs the memory elements by controlling the voltage-current transfer function. The input signals are compared with the respective reference signals by applying voltages corresponding to the input signals in combination with a saturation voltage. The current provided by the memory elements in response to the input signals in the presence of the saturation voltage determines the deviation of the input signal from the reference signal.
The difficulty with the previously described memory elements and matrices of memory elements is that all of these devices or matrices suffer from an electrical instability associated with the thin film semiconducting material of the memory element. That is, the electrical conductivity and the transconductance in either the programmed or non-programmed state of the memory element will drift and decay into an intermediate state over time.
It is also known that ferroelectric materials exhibit a hysteresis effort and such materials have been used to modulate the surface conductivity of semiconductor materials. U.S. Pat No. 2,791,758 to D. H. Looney; U.S. Pat No. 2,791,761 to J. A. Morton; U.S. Pat No. 2,791,759 to W. L. Brown; U.S. Pat No. 2,791,760 to I. M. Hayman and G. H. Hlilmeier, Proceedings of the IEEE, volume 54, number 6 (June, 1966); and "Ceramic Ferroelectric Field Effect Studies" by J. C. Crawford and F. L. English, IEEE Transactions on Electron Devices, volume ed.-16, no. 6 (June, 1969) are believed to be illustrative of the prior art in this respect. One type of these ferroelectric employed a separately grown crystal of guanidinium aluminum sulfate hexahydrate which was placed in contact with the surface of a semiconductor crystal. The air gap between the two surfaces was minimized by various techniques including polishing the surfaces and filling the gap between the surfaces with a dielectric such as ethylene cyanide or nitrobenzene. However, this type of ferroelectric device proved unsatisfactory for many applications due primarily to the poor modulation efficiency of the ferroelectric polarization in combination with a low spontaneous polarization of the guanidinium aluminum sulfate hexahydrate.
As an alternative to forming ferroelectric devices by placing together separately grown ferroelectric and semiconductor crystals, semiconductor films have been deposited by vacuum evaporation on ferroelectric crystals and on ferroelectric ceramic substrates. Generally, these ferroelectric field devices can be divided into categories of an adaptive resistor or an adaptive transistor. The adaptive resistors are fabricated by depositing a semiconducting layer and the adaptive transistors are fabricated by depositing a semiconductive thin film transistor on a ferroelectric crystal or ceramic substrate. Here again, the difficulty with such devices is that they suffer from an electrical instability associated with the thin film semiconducting material. That is, the electrical conductivity and the transconductance in either the programmed or unprogrammed state will drift and decay into an intermediate state with time.
To overcome the problems associated with the thin film semiconducting material, a ferroelectric memory device was developed which utilized the remanent polarization of a ferroelectric thin film to control the surface conductivity of a semiconductor material thereby performing the memory function. The structure of this device is similar to a conventional MOS field effect transistor with the exception that the gate insulating layer is replaced by a layer of an active ferroelectric material. Such a ferroelectric memory device utilizing the remanent polarization of a ferroelectric thin film is described in U.S. Pat. No. 3,832,700. However, this ferroelectric memory device was not compatible with the memory elements used in the matrices employed in the prior art to compare one or more input signals with one or more reference signals.
It remained, therefore, to develop a ferroelectric thin film memory device which would overcome the difficulties and disadvantages of prior art MNOS and ferroelectric memory devices and which was also suitable for use in memory matrices used in the prior art to compare input signals with a reference signal.